product brief august 2000 ATM ph y sical la y er core features n ATM header error correction (hec) byte genera- tion/checking n hec-based cell delineation n cell header single error correction/multiple error detection n cell payload (de)scrambling n direct cell mapping n idle cell insertion/deletion n out of cell delineation (ocd)/loss of cell delinea- tion (lcd) status n user-programmable cell filter n utopia level 1/level 2 with parity generation/ checking. in level 2, all multiphy modes are sup- ported: 1 rxclav/1 txclav direct status multiplexed status polling n 155.52 mbits/s line operation n 25 mhz utopia operation (up to 50 mhz stand-alone utopia) n fifo control/monitoring with options: internal 128 x 9 orca ? fifos (scalable) external 2 n x 9 idt722x1fifos n flexible control inputs with options for: internal/external hard-wiring access via a parallel or serial microprocessor interface standards compliance n ansi* t1.646-1995: broadband-isdn physical layer specification for user-network interface including ds1/ATM n as y nchronous transfer mode ( ATM) forum user- network interface (uni) version 3.1 n ATM forum utopia, an ATM-phy interface speci- fication level 1, version 2.01 n ATM forum utopia level 2, version 1.0 n itu-t recommendation i.432: b-isdn user-net- work interface physical layer specification benefits n faster development for improved time-to-market with ATM functions. n lower development cost through design reuse. n vhdl source code for easy design integration. n orca -specific optimization, tailor made for high performance. n ample design flexibility using built-in interface and function options. n verified functionality and standards compliance. 0378 (f) figure 1. ATM physical layer core application * ansi is a registered trademark of american national standards institute, inc. ATM physical layer core ATM layer line framer (e.g., sonet) optional external fifo optional control/status interface line byte data and clock utopia microprocessor bus
product brief ATM physical layer core august 2000 lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. orca is a registered trademark of lucent technologies inc. foundry is a trademark of xilinx, inc. copyright ? 2000 lucent technologies inc. all rights reserved august 2000 pb00-094ncip for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro , or for fpga information, http://www.lucent.com/orca e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 325 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid) description the ATM physical layer core from modelware* imple- ments, in modular vhdl, the broadband isdn (b-isdn) functions of the transmission convergence (tc) sublayer. the core interfaces to the transmission line via a line framer, and to the ATM layer via a utopia level 1 or level 2 interface (figure 1). the core has the option of using internal or external fifos for cell buffering and timing transfer between the line and the ATM layer. the core using external fifos synthesizes into an or2c/2t15a and the core with two internal 128 x 9 fifos synthesizes into an or2c/2t26a. when imple- mented using a C4 or faster speed orca fpga, the core operates at 19.44 mbytes/s (155.52 mbits/s) on the line side and at 25 mhz on the utopia side. design package the ATM physical layer core package contains: n vhdl source code n vhdl testbench n scripts and data files for simulation (behavioral and gate-level), synthesis, and fpga layout n detailed documentation: reference g uide: features, architecture, inter- faces, and operation user's g uide: simulation, s y nthesis, and fpga la y out procedures required tools n mti ? modelsim ? for simulation n exemplar logic leonardo spectrum for synthesis n lucent technologies orca foundry for fpga layout additional resources n orca ATM physical layer csc application note (ap97-050fpga available from lucent technologies) n orca or2cxxa and or2txxa series field pro- grammable gate arrays data sheet (ds98-140), january 1996 n asynchronous transfer mode: ATM architecture and implementation , martin et al., prentice hall 1996 ordering information modelware, inc. tel: (732) 936-1808 fax: (732) 936-1838 e-mail: sales@modelware.com internet: www.modelware.com * modelware is a registered trademark of modelware, inc. ? mti is a registered trademark of mti technology corporation. ? modelsim is a trademark of mentor grapics corporation. exemplar logic and leonardospectrum are trademarks of exemplar logic, inc.
|
